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1 ltc1742 1742f 14-bit, 65msps low noise adc sample rate: 65msps 76.5db snr and 90db sfdr (3.2v range) 72.8db snr and 90db sfdr (2v range) no missing codes single 5v supply power dissipation: 1.275w selectable input ranges: 1v or 1.6v 240mhz full power bandwidth s/h pin compatible family25msps: ltc1746 (14-bit), ltc1745 (12-bit) 50msps: ltc1744 (14-bit), ltc1743 (12-bit) 65msps: ltc1742 (14-bit), ltc1741 (12-bit) 80msps: ltc1748 (14-bit), ltc1747 (12-bit) 48-pin tssop package telecommunications receivers cellular base stations spectrum analysis imaging systems , ltc and lt are registered trademarks of linear technology corporation. the ltc ? 1742 is an 65msps, sampling 14-bit a/d con- verter designed for digitizing high frequency, wide dy-namic range signals. pin selectable input ranges of 1v and 1.6v along with a resistor programmable mode allow the ltc1742s input range to be optimized for a widevariety of applications. the ltc1742 is perfect for demanding communications applications with ac performance that includes 76.5db snr and 90db spurious free dynamic range. ultralow jitter of 0.15ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 3lsb inl and 1lsb dnl. the digital interface is compatible with 5v, 3v, 2v andlvds logic levels. the enc and enc inputs may be driven differentially from pecl, gtl and other low swing logic families or from single-ended ttl or cmos. the low noise, high gain enc and enc inputs may also be driven by a sinusoidal signal without degrading performance. a separate output power supply can be operated from 0.5v to 5v, making it easy to connect directly to low voltage dsps or fifos. the tssop package with a flow-through pinout simplifies the board layout. 65msps, 14-bit adc with a 2v differential input range 14-bit pipelined adc 14 s/h amp 1v differential analog input a in + a in C sense v cm 4.7 f diff amp refla refhb gnd 1742 bd enc 4.7 f 1 f1 f 0.1 f 0.1 f refha reflb buffer range select 2.35v ref correction logic and shift register output latches control logic ov dd v dd ognd 0.5vto 5v 5v 0.1 f 1 f 1 f 1 f d13d0 clkout of ?? ? enc differential encode input oe msbinv 0.1 f descriptio u features applicatio s u block diagra w downloaded from: http:///
2 ltc1742 1742f parameter conditions min typ max units resolution (no missing codes) 14 bits integral linearity error (note 6) C 3 0.75 3 lsb differential linearity error C1 0.5 1 lsb offset error (note 7) C 35 53 5 m v gain error external reference (sense = 1.6v) C 3.5 1 3.5 %fs full-scale drift internal reference 40 ppm/ c full-scale drift external reference (sense = 1.6v) 20 ppm/ c offset drift internal reference 20 m v/ c input referred noise (transition noise) sense = 1.6v 0.82 lsb rms order part number ov dd = v dd (notes 1, 2) supply voltage (v dd ) ............................................. 5.5v analog input voltage (note 3) .... C 0.3v to (v dd + 0.3v) digital input voltage (except oe) (note 3) ...................................... C 0.3v to (v dd + 0.3v) oe input voltage (note 4) ........ C 0.3v to (ov dd + 0.3v) digital output voltage ................. C 0.3v to (v dd + 0.3v) ognd voltage ..............................................C 0.3v to 1v power dissipation ............................................ 2000mw operating temperature range ltc1742c ............................................... 0 c to 70 c ltc1742i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c ltc1742cfwltc1742ifw t jmax = 150 c, q ja = 35 c/w the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) absolute m axi m u m ratings w ww u package/order i n for m atio n w u u 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 top view fw package 48-lead plastic tssop 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 sense v cm gnd a in + a in C gnd v dd v dd gnd reflb refha gndgnd refla refhb gnd v dd v dd gnd v dd gnd msbinv encenc ofognd d13 d12 d11 ov dd d10 d9d8 d7 ognd gnd gnd d6 d5 d4 ov dd d3d2 d1 d0 ognd clkout oe co verter characteristics u symbol parameter conditions min typ max units v in analog input range (note 8) 4.75v v dd 5.25v 1 to 1.6 v i in analog input leakage current 0 < a in + , a in C < v dd C1 1 m a c in analog input capacitance sample mode enc < enc 8 pf hold mode enc > enc 4 pf t acq sample-and-hold acquisition time 5 7.3 ns t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.15 ps rms cmrr analog input common mode rejection ratio 1.5v < (a in C = a in + ) < 3v 80 db the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) a alog i put u u consult ltc marketing for parts specified with wider operating temperature ranges. downloaded from: http:///
3 ltc1742 1742f parameter conditions min typ max units v cm output voltage i out = 0 2.30 2.35 2.40 v v cm output tempco i out = 0 30 ppm/ c v cm line regulation 4.75v v dd 5.25v 3 mv/v v cm output resistance 1ma ? i out ? 1ma 4 w (note 5) i ter al refere ce characteristics uu u symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input signal (2v range) 72.8 db 5mhz input signal (3.2v range) 75 76.5 db 30mhz input signal (2v range) 72.5 db 30mhz input signal (3.2v range) 74 76.5 db 70mhz input signal (2v range) 72.2 db 70mhz input signal (3.2v range) 75.8 db sfdr spurious free dynamic range 5mhz input signal (2v range) 90 db 5mhz input signal (3.2v range) (2nd and 3rd) 90 db 5mhz input signal (3.2v range) (other) 95 db 30mhz input signal (2v range) 90 db 30mhz input signal (3.2v range) (2nd and 3rd) 80 88 db 30mhz input signal (3.2v range) (other) 85 95 db 70mhz input signal (2v range) 83 db 70mhz input signal (3.2v range) (2nd and 3rd) 75 db 70mhz input signal (3.2v range) (other) 95 db s/(n + d) signal-to-(noise + distortion) ratio 5mhz input signal (2v range) 72.6 db 5mhz input signal (3.2v range) 74.5 76.2 db 30mhz input signal (2v range) 72.3 db 30mhz input signal (3.2v range) 76.0 db 70mhz input signal (2v range) 71 db 70mhz input signal (3.2v range) 71 db thd total harmonic distortion 5mhz input signal, first 5 harmonics (2v range) C90 db 5mhz input signal, first 5 harmonics (3.2v range) C90 db 30mhz input signal, first 5 harmonics (2v range) C90 db 30mhz input signal, first 5 harmonics (3.2v range) C85 db 70mhz input signal, first 5 harmonics (2v range) C78 db 70mhz input signal, first 5 harmonics (3.2v range) C74 db imd intermodulation distortion f in1 = 2.52mhz, f in2 = 5.2mhz (2v range) 97 dbc f in1 = 2.52mhz, f in2 = 5.2mhz (3.2v range) 93 dbc sample-and-hold bandwidth r source = 50 w 240 mhz t a = 25 c. a in = 1dbfs. (note 5) dy a ic accuracy u w downloaded from: http:///
4 ltc1742 1742f symbol parameter conditions min typ max units t 0 enc period (note 9) 15.3 2000 ns t 1 enc high (note 8) 7.3 1000 ns t 2 enc low (note 8) 7.3 1000 ns t 3 aperture delay (note 8) 0 ns t 4 enc to clkout falling c l = 10pf (note 8) 1 2.4 4 ns t 5 enc to clkout rising c l = 10pf (note 8) t 1 + t 4 ns for 65msps 50% duty cycle c l = 10pf (note 8) 8.7 10.1 11.7 ns t 6 enc to data delay c l = 10pf (note 8) 2 4.9 7.2 ns t 7 enc to data delay (hold time) (note 8) 1.4 3.4 4.7 ns t 8 enc to data delay (setup time) c l = 10pf (note 8) t 0 C t 6 ns for 65msps 50% duty cycle c l = 10pf (note 8) 8.2 10.5 13.4 ns t 9 clkout to data delay (hold time), (note 8) 7n s 65msps 50% duty cycle t 10 clkout to data delay (setup time), c l = 10pf (note 8) 3n s 65msps 50% duty cycle t 11 data access time after oe c l = 10pf (note 8) 10 25 ns t 12 bus relinquish (note 8) 10 25 ns data latency 5 cycles the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ti i g characteristics u w symbol parameter conditions min typ max units v dd positive supply voltage 4.75 5.25 v i dd positive supply current 255 275 ma p dis power dissipation 1.275 1.375 w ov dd digital output supply voltage 0.5 v dd v the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) power require e ts w u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v, msbinv and oe 2.4 v v il low level input voltage v dd = 4.75v, msbinv and oe 0.8 v i in digital input current v in = 0v to v dd 10 m a c in digital input capacitance msbinv and oe only 1.5 pf v oh high level output voltage ov dd = 4.75v i o = C10 m a 4.74 v i o = C 200 m a 4 4.74 v v ol low level output voltage ov dd = 4.75v i o = 160 m a 0.05 v i o = 1.6ma 0.1 0.4 v i oz hi-z output leakage d13 to d0 v out = 0v to v dd , oe = high 10 m a c oz hi-z output capacitance d13 to d0 oe = high (note 8) 15 pf i source output source current v out = 0v C 50 ma i sink output sink current v out = 5v 50 ma the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) digital i puts a d digital outputs u u downloaded from: http:///
5 ltc1742 1742f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: all voltage values are with respect to ground with gnd (unless otherwise noted).note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currentsof greater than 100ma below gnd or above v dd without latchup. note 4: when this pin voltage is taken below gnd or above ov dd , it will be clamped by internal diodes. this product can handle input currents of >100ma below gnd or above ov dd without latchup. note 5: v dd = 5v, f sample = 65mhz, differential enc/enc = 2v p-p 65mhz sine wave, input range = 1.6v differential, unless otherwise specified. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.the deviation is measured from the center of the quantization band. note 7: bipolar offset is the offset voltage measured from C 0.5 lsb when the output code flickers between 00 0000 0000 0000 and 111111 1111 1111. note 8: guaranteed by design, not subject to test. note 9: recommended operating conditions. electrical characteristics typical perfor a ce characteristics uw inl, 3.2v range dnl, 3.2v range 8192 point fft,input frequency = 15mhz, 1db, 3.2v range 8192 point fft,input frequency = 15mhz, 10db, 3.2v range 8192 point fft,input frequency = 15mhz, 20db, 3.2v range 8192 point fft,input frequency = 30mhz, 1db, 3.2v range output code 0 C2.5 error (lsb) C2.0 C1.0 C0.5 0 2.51.0 4096 8192 1742 g01 C1.5 1.5 2.0 0.5 12288 16384 t a = 25 c output code 0 C1.0 error (lsb) C0.8 C0.4 C0.2 0 1.00.4 4096 8192 1742 g02 C0.6 0.6 0.8 0.2 12288 16384 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g03 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g04 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g05 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g06 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c downloaded from: http:///
6 ltc1742 1742f typical perfor a ce characteristics uw 8192 point fft,input frequency = 40mhz, 1db, 3.2v range 8192 point fft,input frequency = 40mhz, 10db, 3.2v range 8192 point fft,input frequency = 40mhz, 20db, 3.2v range 8192 point fft,input frequency = 50mhz, 1db, 3.2v range 8192 point fft,input frequency = 30mhz, 20db, 3.2v range 8192 point fft,input frequency = 30mhz, 10db, 3.2v range 8192 point fft,input frequency = 50mhz, 10db, 3.2v range 8192 point fft,input frequency = 50mhz, 20db, 3.2v range 8192 point fft,input frequency = 70mhz, 1db, 3.2v range frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g07 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g08 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g09 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g10 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g11 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g12 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g13 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g14 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g15 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c downloaded from: http:///
7 ltc1742 1742f typical perfor a ce characteristics uw 8192 point 2-tone fft,input frequency = 5mhz and 7mhz, 7db, 3.2v range 8192 point fft,input frequency = 70mhz, 20db, 3.2v range 8192 point fft,input frequency = 70mhz, 10db, 3.2v range 8192 point 2-tone fft, input frequency = 25mhz and 30mhz, 7db, 3.2v range 8192 point 2-tone fft,input frequency = 68mhz and 70mhz, 7db, 3.2v range sfdr vs 15mhz input level sfdr vs 30mhz input level sfdr vs 50mhz input level sfdr vs 70mhz input level frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g16 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g17 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g18 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g19 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c frequency (mhz) 0 amplitude (dbfs) C60 C30 C20 1742 g20 C70 C80 C120 10 20 30 5 15 25 C100 0 C10 C40 C50 C90 C110 t a = 25 c input level (dbfs) C80 sfdr (dbc and dbfs) 60 90 100 0 1742 g21 50 40 0 C60 C40 C20 C70 C50 C30 C10 20 120 110 dbfs t a = 25 c dbc 8070 30 10 input level (dbfs) C80 sfdr (dbc and dbfs) 60 90 100 0 1742 g22 50 40 0 C60 C40 C20 C70 C50 C30 C10 20 120 110 8070 30 10 dbfs dbc t a = 25 c input level (dbfs) C80 sfdr (dbc and dbfs) 60 90 100 0 1742 g23 50 40 0 C60 C40 C20 C70 C50 C30 C10 20 120 110 8070 30 10 dbfs dbc t a = 25 c input level (dbfs) C80 sfdr (dbc and dbfs) 60 90 100 0 1742 g24 50 40 0 C60 C40 C20 C70 C50 C30 C10 20 120 110 8070 30 10 dbfs dbc t a = 25 c downloaded from: http:///
8 ltc1742 1742f typical perfor a ce characteristics uw sfdr vs input frequency andamplitude, 3.2v range, 2nd and 3rd harmonic sfdr vs input frequency andamplitude, 2v range, 2nd and 3rd harmonic shorted input histogram snr vs input frequency3.2v and 2v range snr vs sample rate, 5mhz input, 1db, 3.2v range supply current vs sample rate sfdr vs sample rate, 5mhz input, 1db, 3.2v range input frequency (mhz) 0 sfdr (dbfs) 75 80 85 60 100 1742 g25 70 65 60 20 40 80 90 95 100 C20db C10db C6db C1db t a = 25 c input frequency (mhz) 0 sfdr (dbfs) 75 80 85 60 100 1742 g26 70 65 60 20 40 80 90 95 100 C6db C1db t a = 25 c C10db C20db code 8140 0 count 10000 15000 20000 8144 35000 t a = 25 c 1742 g27 5000 8142 8141 8145 8147 8146 8143 25000 30000 input frequency (mhz) 10 snr (dbfs) 75.0 76.0 3.2v range t a = 25 c 2v range 77.0 80 1742 g28 74.073.0 74.5 75.5 76.573.5 72.5 72.0 71.5 30 60 20 09 0 40 50 70 100 sample rate (msps) 0 72 snr (dbfs) 73 75 76 77 20 40 50 90 1742 g29 74 10 30 60 70 80 78 t a = 25 c sample rate (msps) 0 sfdr (dbfs) 80 85 90 80 1742 g30 75 70 60 20 40 60 10 90 30 50 70 65 100 95 t a = 25 c sample rate (msps) 0 210 supply current (ma) 220 230 240 250 260 270 t a = 25 c 20 40 60 80 1742 g31 downloaded from: http:///
9 ltc1742 1742f uu u pi fu ctio s sense (pin 1): reference sense pin. ground selects 1v. v dd selects 1.6v. greater than 1v and less than 1.6v applied to the sense pin selects an input range of v sense , 1.6v is the largest valid input range. v cm (pin 2): 2.35v output and input common mode bias. bypass to ground with 4.7 m f ceramic chip capacitor. gnd (pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): adc power ground.a in + (pin 4): positive differential analog input. a in (pin 5): negative differential analog input. v dd (pins 7, 8, 17, 18, 20): 5v supply. bypass to agnd with 1 m f ceramic chip capacitors at pin 8 and pin 18. reflb (pin 10): adc low reference. bypass to pin 11 with 0.1 m f ceramic chip capacitor. do not connect to pin? 14. refha (pin 11): adc high reference. bypass to pin 10 with 0.1 m f ceramic chip capacitor, to pin 14 with a 4.7 m f ceramic capacitor and to ground with 1 m f ceramic capacitor. refla (pin 14): adc low reference. bypass to pin 15 with 0.1 m f ceramic chip capacitor, to pin 11 with a 4.7 m f ce- ramic capacitor and to ground with 1 m f ceramic capacitor. refhb (pin 15): adc high reference. bypass to pin 14 with 0.1 m f ceramic chip capacitor. do not connect to pin? 11. msbinv (pin 22): msb inversion control. low inverts the msb, 2s complement output format. high does notinvert the msb, offset binary output format. enc (pin 23): encode input. the input sample starts on the positive edge.enc (pin 24): encode complement input. conversion starts on the negative edge. bypass to ground with 0.1 m f ceramic for single-ended encode signal.oe (pin 25): output enable. low enables outputs. logic high makes outputs hi-z. oe should not exceed thevoltage on ov dd . clkout (pin 26): data valid output. latch data on the rising edge of clkout.ognd (pins 27, 38, 47): output driver ground. d0-d3 (pins 28 to 31): digital outputs. ov dd (pins 32, 43): positive supply for the output driv- ers. bypass to ground with 0.1 m f ceramic chip capacitor. d4-d6 (pins 33 to 35): digital outputs. d7-d10 (pins 39 to 42): digital outputs. d11-d13 (pins 44 to 46): digital outputs. of (pin 48): over/under flow output. high when an over or under flow has occurred. downloaded from: http:///
10 ltc1742 1742f ti i g diagra u ww 1742 td t 3 t 7 t 6 t 4 t 5 t 10 t 9 n ? t 2 t 0 t 1 t 8 data (n C 5) db13 to db0 analog input enc data clkout data (n C 4) db13 to db0 data (n C 3) t 12 t 11 data n db13 to db0, of and clkout oe data applicatio s i for atio wu uu dynamic performancesignal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv v n v = +++ 20 234 1 222 2 ... where v1 is the rms amplitude of the fundamental fre-quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a differentfrequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodulationdistortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. downloaded from: http:///
11 ltc1742 1742f applicatio s i for atio wu uu spurious free dynamic range (sfdr)spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale inputsignal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc equals the enc voltage to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio dueto the jitter alone will be: snr jitter = C20log (2 p ) ? f in ? t jitter converter operationthe ltc1742 is a cmos pipelined multistep converter. the converter has four pipelined adc stages; a sampled analog input will result in a digitized value five cycles later, see the timing diagram section. the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differen- tial input drive will reduce even order harmonics of the sample-and-hold circuit. the encode input is also differential for improved common mode noise immunity. the ltc1742 has two phases of operation, determined by the state of the differential enc/enc input pins. for brev- ity, the text will refer to enc greater than enc as enc high and enc less than enc as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. diff ref amp ref buf 4.7 f 1 f 0.1 f 0.1 f 1 f internal clock signals refl refh differential input low jitter clock driver range select 2.35v reference first pipelined adc stage (5 bits) fourth pipelined adc stage (4 bits) second pipelined adc stage (4 bits) enc refha reflb refla refhb enc shift register and correction oe msbinv ognd of ov dd 0.5v to5v d13d0 clkout 1742 f01 input s/h sense v cm a in C a in + 4.7 f third pipelined adc stage (4 bits) output drivers control logic and calibration logic figure 1. functional block diagram downloaded from: http:///
12 ltc1742 1742f in operation, the adc quantizes the input to the stage andthe quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the sampled input is held. while enc is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of enc. when enc goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is re- peated for the third stage, resulting in a third stage residue that is sent to the fourth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc1742 cmos differential sample-and-hold. the differential ana- log inputs are sampled directly onto sampling capacitors (c sample ) through cmos transmission gates. this direct capacitor sampling results in lowest possible noise for agiven sampling capacitor size. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input.during the sample phase when enc/enc is low, the transmission gate connects the analog inputs to the sam- pling capacitors and they charge to, and track the differen- tial input voltage. when enc/enc transitions from low to high the sampled input voltage is held on the samplingcapacitors. during the hold phase when enc/enc is high the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc/enc transitions from high to low the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve specified performance. each input should swing 0.8v for the 3.2v range or 0.5v for the 2v range, around a common mode voltage of 2.35v. the v cm output pin (pin? 2) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op ampdifferential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 4.7 m f or greater capacitor. applicatio s i for atio wu uu c sample 4pf v dd ltc1742 a in + 1742 f02 c sample 4pf bias v dd 5v a in C enc enc 2v 6k 2v 6k c parasitic 4pf c parasitic 4pf figure 2. equivalent input circuit downloaded from: http:///
13 ltc1742 1742f input drive impedanceas with all high performance, high speed adcs the dy- namic performance of the ltc1742 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can influence sfdr. at the falling edge of encode the sample- and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when encode rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capaci- tor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling maydegrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recomended to have a source impedence of 100 w or less for each input. the s/h circuit is optimized for a 50 w source impedance. if the source impedance is less than 50 w , a series resistor should be added to increase this impedance to 50 w . the source impedence should be matched for the differentialinputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc1742 being driven by an rftransformer with a center tapped secondary. the second- ary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turnsratio transformer. other turns ratios can be used if the source impedence seen by the adc does not exceed100 w for each adc input. a disadvantage of using a transformer is the loss of low frequency response. mostsmall rf transformers have poor performance at frequen- cies below 1mhz. figure 4 demonstrates the use of operational amplifiers toconvert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies. the 25 w resistors and 12pf capacitors on the analog inputs serve two purposes: isolating the drive circuitryfrom the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequencies higher than 100mhz, the capacitors may need to be decreased to prevent excessive signal loss. reference operation figure 5 shows the ltc1742 reference circuitry consisting of a 2.35v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage refer- ence can be configured for two pin selectable input ranges of 2v( 1v differential) or 3.2v( 1.6v differential). tying the sense pin to ground selects the 2v range; tying the sense pin to v dd selects the 3.2v range. the 2.35v bandgap reference serves two functions: itsoutput provides a dc bias point for setting the common applicatio s i for atio wu uu 1:1 25 0.1 f analog input v cm a in + a in C 100 100 12pf 12pf 12pf 1742 f03 4.7 f 25 25 25 ltc1742 25 5v single-ended input 2.35v 1/2 range v cm a in + a in C 12pf 12pf 12pf 1742 f04 4.7 f 25 100 500 500 25 25 ltc1742 C + 1/2 lt1810 C + 1/2 lt1810 figure 4. differential drive with op amps figure 3. single-ended to differential conversionusing a transformer downloaded from: http:///
14 ltc1742 1742f mode voltage of any external input circuitry; additionally,the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 2.35v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external cir-cuitry. this is also the compensation capacitor for the reference. it will not be stable without this capacitor. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins: refha and refhb for the high reference and refla and reflb for the low reference. the doubled output pins are needed to reduce package inductance. bypass capacitors must be con- nected as shown in figure 5. other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in figure 6a. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device since the logic threshold is close to ground and v dd . the sense pin should be tied high or low as close to the converter as possible. if the sense pin is drivenexternally, it should be bypassed to ground as close to the device as possible with a 1 m f ceramic capacitor. input rangethe input range can be set based on the application. for oversampled signal processing in which the input fre- quency is low (<10mhz), the largest input range will provide the best signal-to-noise performance while main- taining excellent sfdr. for high input frequencies (> 40mhz), the 2v range will have the best sfdr perfor- mance for the 2nd and 3rd harmonics, but the snr will degrade by 3.5db. see the typical performance charac- teristics section. driving the encode inputs the noise performance of the ltc1742 can depend on the encode signal quality as much as on the analog input. the enc/enc inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 2v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. applicatio s i for atio wu uu v cm refha reflb sense tie to v dd for 3.2v range; tie to gnd for 2v range; range = 2 ? v sense for 1v < v sense < 1.6v 2.35v refla refhb 4.7 f 4.7 f internal adchigh reference buffer 0.1 f 1742 f05 ltc1742 4 diff amp 1 f 1 f 0.1 f internal adclow reference 2.35v bandgap reference 1.6v 1v range detect and control figure 5. equivalent reference circuit v cm sense 2.35v 1.1v 4.7 f 12.5k 1 f 11k 1742 f06a ltc1742 v cm sense 2.35v 5v 1.25v 6 4 1, 2 4.7 f 1 f 0.1 f 1742 f06b ltc1742 lt1790-1.25 figure 6a. 2.2v range adc figure 6b. 2.5v range adc with external reference downloaded from: http:///
15 ltc1742 1742f any noise present on the encode signal will result inadditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies) take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase theamplitude. 3. if the adc is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear atboth inputs as common mode noise. applicatio s i for atio wu uu v dd ltc1742 1742 f07 bias v dd 5v enc enc analog input 2v bias 2v bias 1:4 0.1 f clock input 50 6k 6k to internaladc circuits figure 7. transformer driven enc/enc 1742 f08a enc 2v v threshold = 2v enc 0.1 f ltc1742 1742 f08b enc enc 130 3.3v 3.3v 130 d0 q0 q0 mc100lvelt22 ltc1742 83 83 figure 8a. single-ended enc drive, not recommended for low jitter figure 8b. enc drive using a cmos-to-pecl translator the encode inputs have a common mode range of 1.8v tov dd . each input may be driven from ground to v dd for single-ended drive.maximum and minimum encode rates the maximum encode rate for the ltc1742 is 65msps. for the adc to operate properly the encode signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 7.3ns for the adc internal circuitry to have enough settlingtime for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. downloaded from: http:///
16 ltc1742 1742f at sample rates slower than 65msps the duty cycle canvary from 50% as long as each half cycle is at least 7.3ns. the lower limit of the ltc1742 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating fre- quency for the ltc1742 is 1msps. digital outputs digital output buffers figure 9 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additionaln-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 w to external circuitry and may eliminate the need for external dampingresistors. output loading as with all high speed/high resolution converters the digital output loading can affect the performance. the digital outputs of the ltc1742 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the applicatio s i for atio wu uu output may be used but is not required since the adc hasa series resistor of 43 w on chip. lower ov dd voltages will also help reduce interference from the digital outputs.format the ltc1742 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the msbinv pin; high selects offset binary. overflow bit an overflow output bit indicates when the converter is overranged or underranged. when of outputs a logic high the converter is either overranged or underranged. output clock the adc has a delayed version of the enc input available as a digital output, clkout. the clkout pin can be used to synchronize the converter data to the digital system. this is necessary when using a sinusoidal encode. data will be updated just after clkout falls and can be latched on the rising edge of clkout. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. forexample if the converter is driving a dsp powered by a 3v supply then ov dd should be tied to that same 3v supply. ltc1742 1742 f09 ov dd v dd v dd 0.1 f 43 typical data output ognd ov dd 0.5v tov dd predriver logic data from latch oe figure 9. equivalent circuit for a digital output buffer downloaded from: http:///
17 ltc1742 1742f applicatio s i for atio wu uu ov dd can be powered with any voltage up to 5v. the logic outputs will swing between ognd and ov dd . output enablethe outputs may be disabled with the output enable pin, oe. oe low disables all data outputs including of and clkout. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. the voltage on oe can swing between gnd and ov dd . oe should not be driven above ov dd . grounding and bypassingthe ltc1742 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an inter- nal ground plane is recommended. the pinout of the ltc1742 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , refha, refhb, refla and reflb pins as shown in the block diagram on the front page of this datasheet. bypass capacitors must be located as close to the pins as possible. of particular importance are the capaci- tors between refha and reflb and between refhb and refla. these capacitors should be as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recomended. the large 4.7 m f capacitor between refha and refla can be somewhat further away. the tracesconnecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1742 differential inputs should run parallel andclose to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. an analog ground plane separate from the digital process- ing system ground should be used. all adc ground pins labeled gnd should connect to this plane. all adc v dd bypass capacitors, reference bypass capacitors and inputfilter capacitors should connect to this analog plane. the ltc1742 has three output driver ground pins, labeled ognd (pins 27, 38 and 47). these grounds should con- nect to the digital processing system ground. the output driver supply, ov dd should be connected to the digital processing system supply. ov dd bypass capacitors should bypass to the digital system ground. the digital process-ing system ground should be connected to the analog plane at adc ognd (pin 38). heat transfer most of the heat generated by the ltc1742 is transferred from the die through the package leads onto the printed circuit board. in particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. these pins have the lowest thermal resistance between the die and the outside envi- ronment. it is critical that all ground pins are connected to a ground plane of sufficient area. the layout of the evalu- ation circuit shown on the following pages has a low ther- mal resistance path to the internal ground plane by using multiple vias near the ground pins. a ground plane of this size results in a thermal resistance from the die to ambient of 35 c/w. smaller area ground planes or poorly connected ground pins will result in higher thermal resistance. downloaded from: http:///
18 ltc1742 1742f applicatio s i for atio wu uu c44.7 f c3 10 f r5 1 34 12 5v u3 lt1521-3 r n5a 33 r9 33 r n5b 33 r n5c 33 r n5d 33 r n6a 33 r n6b 33 r n6c 33 r n6d 33 r n7a 33 r n7b 33 r n7c 33 r n7d 33 r n8a 33 r n8b 33 r n8c 33 c12 0.1 f c10 0.1 f of ognd d13d12 d11 ov dd d10 d9d8 d7 ognd gndgnd d6d5 d4 ov dd d3d2 d1 d0 ognd clkout oe sensev cm gnda in + a in C gndv dd v dd gndreflb refha gnd gnd refla refhb gnd v dd v dd gndv dd gndmsbinv enc enc 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 2oe2q8 2q7 gnd 2q62q5 v cc 2q42q3 gnd 2q22q1 1q8 1q7 gnd 1q61q5 v cc 1q41q3 gnd 1q21q1 1oe 2le2d8 2d7 gnd 2d6 2d5 v cc 2d42d3 gnd 2d2 2d1 1d8 1d7 gnd 1d6 1d5 v cc 1d41d3 gnd 1d2 1d1 1le 2423 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2526 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 u4 p174vcx16373v u5 ltc1742 c190.1 f c200.1 f c210.1 f c220.1 f 1742 ta01 c280.1 f j2 3201s-40g1 3v 3v clkoutclkout u2 10t74alvc1g86 jp2 13 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 24 6 8 1012 14 16 18 20 22 24 26 28 30 32 34 36 38 40 in tab out gnd c12 f c230.1 f c1610 f e1 5v e4 pgnd jp4 jp3 5v input range select twos complement select r y * c2412pf c25 12pf *rx, ry = optional input range set **do not install r1 and r10 j1 optional +input j4 optional C input encode input j3 analog input c512pf c29 1 f r1** 0 r10** 0 r2 24.9 t1 minicircuits t1-1t r4100 r3100 ?? r8 0 r22100 t2 minicircuits t1-1t ?? r21100 jp5 optional xtal clk r7 24.9 j5 c8 4.7 f c13 0.1 f c18 4.7 f r b 24.9 r a 24.9 c26 0.1 f c7 0.1 f c8 4.7 f c90.1 f c27 0.1 f c15 0.1 f r x * c14 4.7 f c32 30pf c111 f c2 0.1 f r6 200 jp1 c31 0.1 f c170.1 f c30 0.1 f 5v 1411 8 7 4 1 e3 gnd e4 gnd e5 gnd y1 evaluation circuit schematic of the ltc1742 downloaded from: http:///
19 ltc1742 1742f applicatio s i for atio wu uu silkscreen top layer 1 component side layer 2 gnd plane layer 3 power plane layer 4 solder side information furnished by linear technology corporation is believed to be accurate and reliable.however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
20 ltc1742 1742f ? linear technology corporation 2003 lt/tp 0603 1k ? printed in the usa part number description comments ltc1405 12-bit, 5msps sampling adc with parallel output pin compatible with the ltc1420 ltc1406 8-bit, 20msps adc undersampling capability up to 70mhz ltc1411 14-bit, 2.5msps adc 5v, no pipeline delay, 80db sinad ltc1412 12-bit, 3msps, sampling adc 5v, no pipeline delay, 72db sinad ltc1414 14-bit, 2.2msps adc 5v, 81db sinad and 95db sfdr ltc1420 12-bit, 10msps adc 71db sinad and 83db sfdr at nyquist lt ? 1461 micropower precision series reference 0.04% max initial accuracy, 3ppm/ c drift ltc1666 12-bit, 50msps dac pin compatible with the ltc1668, ltc1667 ltc1667 14-bit, 50msps dac pin compatible with the ltc1668, ltc1666 ltc1668 16-bit, 50msps dac 16-bit, no missing codes, 90db sinad, C100db thd ltc1741 12-bit, 65msps adc pin compatible with the ltc1742 ltc1743 12-bit, 50msps adc pin compatible with the ltc1742 ltc1744 14-bit, 50msps adc pin compatible with the ltc1742 ltc1745 12-bit, 25msps adc pin compatible with the ltc1742 ltc1746 14-bit, 25msps adc pin compatible with the ltc1742 ltc1747 12-bit, 80msps adc pin compatible with the ltc1742 ltc1748 14-bit, 80msps adc pin compatible with the ltc1742 lt1807 325mhz, low distortion dual op amp rail-to-rail input and output related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com package descriptio u fw package 48-lead plastic tssop (6.1mm) (reference ltc dwg # 05-08-1651) fw48 tssop 0502 0.09 C 0.20 (.0035 C .008) 0 C 8 0.45 C 0.75 (.018 C .029) 0.17 C 0.27 (.0067 C .0106) 0.50 (.0197) bsc 6.0 C 6.2** (.236 C .244) 7.9 C 8.3 (.311 C .327) 134 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 12.4 C 12.6* (.488 C .496) 1.20 (.0473) max 0.05 C 0.15 (.002 C .006) 2 48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 47 c.10 -t- -c- millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per sidedimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale * ** 0.32 0.05 0.50 typ 6.2 0.10 8.1 0.10 recommended solder pad layout 0.95 0.10 downloaded from: http:///

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